Electronic memory devices comprising non-volatile cells are largely used in multiple apparatuses where storing a great amount of information in a compact support is required, such as in cell phones, digital cameras and notebooks, for example.
In recent years, the circuit architecture of memory devices with non-volatile cells, combined with advanced technological processes, have resulted in the operational characteristics of the devices to be improved in terms of the write, read and erase speeds of the single memory cells.
The straightforward and reduced structure of the cells of the NAND type is suitable for realizing memory devices of the Flash NAND type having a high integration density. Memory devices with Flash NAND cells are semiconductor integrated devices, and comprise a plurality of memory cells that are organized in a matrix. The matrix of memory cells are organized in rows called word lines WL and columns called bit lines BL.
The particular matrix-like configuration of these non-volatile memory devices is key to obtaining the desired technical characteristics. The memory cells are floating gate transistors and they have a region of conductive material, insulated by a dielectric oxide, above which a control gate is overlapped. Everything is arranged above a channel region of the transistor.
According, for example, to a NAND architecture, the memory cells are arranged in series or strings and thus the sole contacts for a series of cells belong to the same bit lines, which are normally 16 or 32 cells. The contacts are on the drain of the drain select transistor DSL and on the source of the source select transistor SSL. Along the series the drain of the n-th cell is physically connected (same diffusion) to the source of the cell preceding it (n−1). The source of the cell (n) is in common with the drain of the successive cell (n+1). Thus, the drain and source electrodes of the single cells are not singularly accessible. Through metal electrodes connected to a body of each cell, predetermined voltage values are applied to the memory cell making it operative.
The charge stored in the floating gate region determines the logic state of the cell, modifying its threshold voltage. The fundamental characteristic of a memory cell is that of having two states, one with a low threshold voltage which, according to the convention, is given the value 0 or 1, and one with a high threshold voltage is given the is given the value 1 or 0. The voltage is externally applied through the control gate.
The need of storing, in a more reduced space, a greater amount of data has led to the development of devices with multilevel memory cells where, in each cell, different logic states are stored.
The high integration required for memory devices and thus the reduced space between the floating gates of opposite cells, arranged on consecutive word lines, makes it a fundamental importance for the accurate control of the distributions of the thresholds in the single cells so as to correctly position the cell at the programmed voltage value. In the devices with multilevel memory cells, the control of the thresholds in the single cells is even more important since the different levels are separated-within narrow voltage ranges.
The architecture of a Flash NAND memory includes, as highlighted in FIG. 1, an array 1 or matrix, a row and column decoder 2, a page buffer 3, a microcontroller 4 or other logic circuits such as control logics or state machines, and analog and digital circuits.
The architecture of the elements forming the array 1 is highlighted in FIG. 2. The base element of the array is a series or string 6 of cells 7 connected to a definite bit line BLn, and is between a drain selector DSL and a source selector SSL. The string can contain, for example, 16 or 32 cells 7 in series.
The group of cells between the two drain and source select transistors DSL and SSL, and belonging to all the bit lines BLs, with s between 1 and n, of the matrix define a sector or block. The cells 7 of the same sector or block share, according to the architecture, 16 or 32 word lines WL. The group of the sectors or blocks defines the array 1 or matrix.
The biases of the word lines WL, the bit lines BL and the well or body terminal in the single sectors of the matrix differ according to the operation to be performed in each cell: programming, reading or erasing. The programming and the erasing of the Flash NAND memory devices occur by a procedure called Flowler-Nordheim tunneling.
In a programming operation of a memory cell, a known method, indicated by way of example in the table of FIG. 3, provides 0V at the bit line BL of the cell to be programmed, 0V at the body of the cell to be programmed Vwell=0V to suitably enhance the voltage of the cell gate, i.e., of the-selected word line leading it for example to a value equal to 18V, with respect to 10V to which the non-selected word lines of the same selected block are brought.
The logic state of the other cells belonging to the same sector of the cell to be programmed, but not involved in the programming, is kept unaltered by inhibiting the corresponding bit lines, i.e., keeping them at a voltage value equal to VBL=Vcc. This causes a boosting effect in the channels of the non-selected cells, in which the VWLunselected=Vprogram voltage is about 20V in the example.
The read operation of a memory cell, i.e., interpreting the information contained in the cell, occurs through the conductivity or non-conductivity of the cell itself. The method places the voltage of the bit line to be read at a pre-charge value which, in this case, is for example Vcc, with VBLselect=Vcc. The voltage value of the other bit lines VBLunselect is 0V, the voltage value of the selected word line VWLselect is 0V, the value of the other word lines VWLunselect is for example 4.5V, and the value of the body voltage Vwell is 0V.
An erase operation for Flash NAND memory devices has the advantage that it can be carried out by block or sector. In this case the method places the voltage of all the floating bit lines VBLselect=VBLunselect=Vfloat, the voltage of the selected word line at 0V, VWLselect at 0V, the voltage of the other word lines VWLunselect at Vfloat and the body voltage Vwell for example at 20V.
During the programming of a cell in a memory device a lot of attention has been paid to the presence of disturbances, which can both influence the voltage value stored in the single cell to be programmed, and cause a variation of the voltages stored in the adjacent cells.
In the devices with non-volatile memory cells the undesired capacitive couplings between the cells are among the main factors responsible for the disturbances and the so-called “widening of the distributions”. In multilevel devices “the widening of the disturbances” is more dangerous since the thresholds relative to the different levels or logic states are separated within narrow voltage ranges.
In a memory of the Flash NAND type, with a high density, the main parasitic capacitive components are identified, with reference to FIGS. 7 and 8, with the capacitances along:
1. the direction Y of the bit lines;
2. the direction X of the word lines; and
3. direction XY diagonal couplings.
The three identified parasitic capacitances take different values from each other and typically, in the order indicated, they have decreasing values.
The presence of these parasitic capacitances creates serious problems. In fact, they tend to modify the voltages in the cells, and in particular, during the programming operation.
With particular reference to FIG. 4, during the programming of the centrally arranged cell the floating gate voltage of this cell can, as an effect of the parasitic capacitances which are formed with the floating gates of the adjacent cells, be modified. The presence of the parasitic capacitances is due to the geometry of the cells, to the lithography and to the presence of the dielectric placed between the opposite word lines. This is in combination with the limited distance from one another due to the high integration degree of the cells in these devices.
A summary scheme of the parasitic capacitances present in a device is indicated in FIG. 6. From suitable measurements it has been possible to observe how the total of the voltage variation Vth of a cell, due to all the parasitic capacitances of the surrounding cells, erased with voltage for example equal to 20V and programmed with method ISPP, i.e., with the same values of ΔVstep=0.5V and tstep=20 μs, is about 500 mV. The main part of the voltage variation Vth of a cell is mainly due to the contribution of the capacitive couplings along the bit lines, i.e., along the direction Y.
This confirms how the value of the parasitic capacitances, which are created along the bit lines, significantly influences the threshold voltage of the single cells, and thus the correctness of the programmable and programmed values.